ARM Launches Level 2 Cache Controller

Motorola, Inc. was the lead partner in the definition of the L210 controller and is the first ARM Partner to license it. The ARM L210 controller will be incorporated into Motorola's Mobile Extreme Convergence (MXC) architecture for 2.5G, 2.75G and 3G mobile handsets and a new category of portable multimedia devices. MXC incorporates an ARM1136JF-S(TM) core together with the ARM L210 Level 2 cache controller.

Motorola has been using the ARM architecture in its products for more than three years, enabling the company to develop advanced high-end mobile devices. Motorola worked closely with ARM to define the optimal cache controller used in the MXC architecture. The addition of this enhanced memory subsystem typically increases the performance by 25 to 75 percent.

When incorporated into Motorola's MXC architecture, the ARM L210 controller enhances performance to meet growing consumer demand for powerful next-generation handsets that maintain optimal levels of battery life. By concentrating all of the modem processing onto a single DSP (single core modem), the MXC architecture is designed to free up the MCU core to enable richer feature sets across a wide range of mobile devices; simplify the software development environment; accelerate time to market; simplify and reduce inter-processor communications; enable increased efficiency via shared and reduced memory requirements; and provide seamless mobility in a small footprint, with low system and development costs.

"This advancement builds on ARM's high performance road map to extend our strength in performance-driven market segments such as the consumer entertainment and wireless markets," said Bruce Beckloff, director of Segment Marketing, ARM. "With the addition of the L210 cache controller to a system, ARM enables our Partners to realise the power of our high performance cores, such as the ARM1136JF-S core in the 550 MHz range, without having to implement an expensive and complex memory system that would increase system cost and power consumption."

The L210 cache controller reduces the external memory bandwidth requirement of very high-performance CPUs like the ARM1136JF-S core, by requiring fewer CPU memory accesses to go to off-chip memory. It uses a unified instruction and data cache, supporting level two cache sizes from 128k to 2MB. The L210 controller is compatible with the ARM1136JF-S core, the ARM1136J-S(TM) core, the ARM1026EJ-S(TM) core, and the ARM926EJ-S core.

The ARM L210 level 2 cache controller is available for licensing from ARM immediately.

About ARM

ARM is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals, and system-on-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM's microprocessor cores are rapidly becoming a volume RISC standard in such markets as portable communications, hand-held computing, multimedia digital consumer and embedded solutions. More information on ARM is available at http://www.arm.com/ .

NOTE: ARM and ARM Powered are registered trademarks of ARM Limited. ARM926EJ-S, ARM1026EJ-S, ARM1136J-S, ARM1136JF-S and L210 are trademarks of ARM Limited. "ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC; ARM KK; ARM Korea Ltd; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; and ARM Belgium N.V.

CONTACT: Michelle Spencer of ARM, +44-1628-427780, or
Michelle.Spencer@arm.com; or Matthew Rodriguez of Text 100, +1-415-593-8479,
or mrodriguez@text100.com, for ARM; or Stephanie Sobotik of Motorola, Inc.,
+1-512-895-3836, or stephanie.sobotik@motorola.com

Web site: http://www.arm.com/